ECE 252 / CPS 220 - Advanced Computer Architecture I

ECE 252 / CPS 220

Advanced Computer Architecture I

Fall 2007

Professor Daniel J. Sorin

Objectives

The objective of this course is to learn the fundamental aspects of computer architecture design and analysis.

The course focuses on processor design, pipelining, superscalar, out-of-order execution, caches (memory hierarchies), virtual memory, storage

systems, and simulation techniques. Advanced topics include a survey of parallel architectures and future directions in computer architecture.

Prerequisites: ECE 152, CPS 104, or consent of instructor.

Class Location and Hours

Class meets Monday/Wednesday/Friday from 10:20am - 11:10am.

Location: 115A Hudson Hall

Instructor, Teaching Assistant, and News Group

Professor Daniel J. Sorin

Office: 209C Hudson Hall

Office Hours: Tuesday 2-3pm, Wednesday 11:15am (after class)-12:15pm

Email: sorin AT ee DOT duke DOT edu (email subject must begin with ECE252)

Teaching Assistant: Albert Meixner

Office: D311 LSRC

Office Hours: Friday 3-4pm

Email: albert AT cs DOT duke DOT edu

Required Textbook

Computer Architecture: A Quantitative Approach, 4th edition, by Hennessy and Patterson

Assignments and Grading

This course will require readings from the textbooks and from selected research papers. While you will not be quizzed on readings, you

should still be certain to have read them before class so that you can learn from the class. And, to appeal to your practical side, all readings are

fair game for the exams. Added bonus: you will be better at reading research papers at the end of this class than at the beginning.

Students are responsible for:

homework - 30% of grade
midterm exam - 15% of grade
final exam - 25% of grade
individual or group project (including proposals and presentations) - 30% of grade

Note to Computer Science students: Qualifying grade is based only on the midterm and final.

Late policy for homework and project (except for dean's excuses):

Homework: <1 day late = 50% off

>1 day late = 0

Project: No late projects will be accepted!

Academic Misconduct: I will not tolerate academically dishonest work. This includes cheating on the exams and plagiarism on the project.

Be careful on the project to cite prior work and to give proper credit to others' research.

Refer to the Duke Undergraduate Honor Code or to the instructor if you have any questions about misconduct.

Topics, Lecture Notes, and Reading Assignments (still in flux!!)

I will post lecture notes (in PDF format) shortly before I cover them in class. Click on topic title for link to notes.

Readings in blue will be provided by the instructor (click on links below for PS or PDF).

A list of non-required papers on commercial microprocessors

Topic	Reading Assignments
Course Introduction & Computer Performance	H/P Chapter 1; "Instruction Sets and Beyond: Computers, Complexity, and Controversy"
Pipelined Processors	H/P Appendix A; "The Optimal Pipeline Depth Per Pipeline Stage is 6-8 FO4 Inverter Delays"
Hardware/Dynamic Exploitation of Instruction Level Parallelism Superscalar Execution Dynamic Scheduling: Scoreboard and Tomasulo Dynamic Scheduling: Speculation and Precise Interrupts	H/P 2 and 3 (3 is optional); "The Microarchitecture of the Pentium 4 Processor"; "Complexity-Effective Superscalar Processors"; "Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors"
Software/Static Exploitation of Instruction Level Parallelism	H/P Chapter 2; "EPIC: Explicitly Parallel Instruction Computing"
Advanced Cache/Memory Designs	H/P Chapter 5; "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches"; "A Fully-Associative Software-Managed Cache Design"; "Exceeding the Dataflow Limit via Value Prediction"
Multithreading, Multicore, and Multiprocessors Motivations: Power Efficiency, ILP Limits, and TLP Multithreading Multicore Processors	H/P Chapter 4 (and 3.5); "Power: A First Class Design Constraint"; "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor"; "Multiscalar Processors"; "Niagara: A 32-Way Multithreaded SPARC Processor":
Advanced Topics: Fault Tolerance, Virtual Machines, Security, Grid Processors, Nanocomputing	"DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design"; "Virtual Machine Monitors: Current Techology and Future Trends"; "RIFLE: An Architectural Framework for User-Centric Information-Flow Security"; "A Design Space Evaluation of Grid Processor Architectures"; "NANA: A Nano-scale Active Network Architecture"

Homework

Homework policy: Each homework should be done in a group of 2 students. The groups for each homework MUST BE DIFFERENT (you can't work with the same person more than once). For each homework, each group turns in ONE assignment to be graded. This assignment should have the names of both students on it. For electronic submission of simulator code (for some homework questions), one member of the group should upload code.

Homework #1: Due Weds, Sept 12

Homework #2: Due Weds, Sept 26

Homework #3: Due Friday, Oct 12

Homework #4: Due Friday, Nov 2

Homework #5: Due Monday, Nov 19

Project

The course project will be performed either individually or in groups of 2 or 3.

Projects will explore a micro-architectural issue (of your choice) using SimpleScalar. You will be expected to modify the code in sim-outorder as part of your project. See Prof. Sorin for project guidelines and ideas.

Project proposals (2 pages max!!): Due Monday, Oct 15. Proposals must contain the following information:

goal of the project
how the experiments will be performed
timeline for expected project milestones
brief summary of related research papers (with appropriate references!)

Project reports (15 pages max!!): Due Monday, Dec 3 in class. No exceptions!

Schedule (tentative)

This is a tentative schedule which may change depending on time constraints and which days the instructor will be out of town.

Week	Monday	Wednesday	Friday
Aug 27	Intro/Performance	Performance	Pipelining
Sept 3	Pipelining	Pipelining	Pipelining
Sept 10	Dynamic ILP	Dynamic ILP	Dynamic ILP
Sept 17	Dynamic ILP	Dynamic ILP	Dynamic ILP
Sept 24	Dynamic ILP	Dynamic ILP	Dynamic ILP
Oct 1	Static ILP	Static ILP	Static ILP
Oct 8	FALL BREAK	Cache/Memory	Cache/Memory
Oct 15	Cache/Memory	REVIEW FOR MIDTERM	MIDTERM
Oct 22	Cache/Memory	Cache/Memory	Multithreading
Oct 29	Multithreading	Multicore	Multicore
Nov 5	Multicore	Multicore	Fault Tolerance
Nov 12	Fault Tolerance	Virtual Machines	Virtual Machines
Nov 19	Security	THANKSGIVING BREAK
Nov 26	Grid Processors	Nanocomputing	REVIEW FOR FINAL
Dec 3	PROJECT PRESENTATIONS
Dec 10	*-------- EXAM WEEK --------*