The output of the timer is sent to the J-K flip flop.
The J-K flip flop is also a TTL digital logic circuit.
A J-K flip flop may be used to perform many different functions.
In this circuit the J-K flip flop is being used as a frequency divider.
The frequency of the output signal is related to the input frequency by Equation
.
The J-K flip flop requires the input signal to complete one full cycle in order for its output to change states from 0V to 5V or from 5V to 0V. Therefore, it takes 2 periods of the input signal to produce one period at the output of the flip flop.
