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Publications by Alvin R. Lebeck

Papers Published

  1. Patwardhan, J.P. and Johri, V. and Dwyer, C. and Lebeck, A.R., A defect tolerant self-organizing nanoscale SIMD architecture, Comput. Archit. News (USA) Proceedings of ASPLOS 2006, (2006), 241 - 51, [1168919.1168888], [abs]
  2. Pistol, C. and Lebeck, A.R. and Dwyer, C., Design automation for DNA self-assembled nanostructures, 2006 Design Automation Conference (IEEE Cat. No. 06CH37797), (2006), 919 - 24, [abs]
  3. Patwardhan, J.P. and Dwyer, C. and Lebeck, A.R., Self-assembled networks: control vs. complexity, 2006 1st International Conference on Nano-Networks and Workshops (IEEE Cat. No. 06EX1380), (2006), 49 - 53, [abs]
  4. Park, S.H. and Pistol, C. and Ahn, S.J. and Reif, J.H. and Lebeck, A.R. and Dwyer, C. and LaBean, T.H., Erratum: Finite-size, fully addressable DNA tile lattices formed by hierarchical assembly procedures (Angewandte Chemie-International Edition (2006) 45 (735-739)), Angewandte Chemie - International Edition, (2006), 6607 -, [anie.200503797],
  5. Li, T. and Lebeck, A.R. and Sorin, D.J., Spin detection hardware for improved management of multithreaded systems, IEEE Trans. Parallel Distrib. Syst. (USA), (2006), 508 - 21, [78], [abs]
  6. Tong Li and Ellis, C.S. and Lebeck, A.R. and Sorin, D.J., Pulse: a dynamic deadlock detection mechanism using speculative execution, Proceedings of the General Track. 2005 USENIX Annual Technical Conference, (2005), 31 - 44, [abs]
  7. Dwyer, C. and Lebeck, A.R. and Sorin, D.J., Self-assembled architectures and the temporal aspects of computing, Computer (USA), (2005), 56 - 64, [34], [abs]
  8. Zeng, H. and Ellis, C.S. and Lebeck, A.R., Experiences in managing energy with ECOSystem, IEEE Pervasive Comput. (USA), (2005), 62 - 8, [abs]
  9. Xiaobo Fan and Ellis, C.S. and Lebeck, A.R., The synergy between power-aware memory systems and processor voltage scaling, Power-Aware Computer Systems. Third International Workshop, PACS 2003. Revised Papers (Lecture Notes in Computer Science Vol.3164), (2004), 164 - 79, [abs]
  10. Patwardhan, J.P. and Lebeck, A.R. and Sorin, D.J., Communication breakdown: analyzing CPU usage in commercial Web workloads, 2004 IEEE International Symposium on Performance Analysis of Systems and Software (IEEE Cat. No.04EX818), (2004), 12 - 19, [ISPASS.2004.1291351], [abs]
  11. Dwyer, C. and Johri, V. and Cheung, M. and Patwardhan, J. and Lebeck, A. and Sorin, D., Design tools for a DNA-guided self-assembling carbon nanotube technology, Nanotechnology, (2004), 1240 - 1245, [022], [abs]
  12. Thottethodi, M. and Lebeck, A.R. and Mukherjee, S.S., Exploiting global knowledge to achieve self-tuned congestion control for k-ary n-cube networks, IEEE Trans. Parallel Distrib. Syst. (USA), (2004), 257 - 72, [TPDS.2004.1264810], [abs]
  13. Fan, X. and Ellis, C.S. and Lebeck, A.R., Modeling of DRAM power control policies using deterministic and stochastic Petri nets, Power-Aware Computer Systems. Second International Workshop, PACS 2002. Revised Papers (Lecture Notes in Computer Science Vol.2325), (2003), 130 - 40, [abs]
  14. Heng Zeng and Ellis, C.S. and Lebeck, A.R. and Vahdat, A., Currentcy: a unifying abstraction for expressing energy management policies, General Track 2003 USENIX Annual Technical Conference, (2003), 43 - 56, [abs]
  15. Thottethodi, M. and Lebeck, A.R. and Mukherjee, S.S., BLAM: a high-performance routing algorithm for virtual cut-through networks, Proceedings International Parallel and Distributed Processing Symposium, (2003), 10 pp. -, [IPDPS.2003.1213133], [abs]
  16. Chatterjee, S. and Lebeck, A.R. and Patnala, P.K. and Thottethodi, M., Recursive array layouts and fast matrix multiplication, IEEE Trans. Parallel Distrib. Syst. (USA), (2002), 1105 - 23, [TPDS.2002.1058095], [abs]
  17. Heng Zeng and Ellis, C.S. and Lebeck, A.R. and Vahdat, A., ECOSystem: managing energy as a first class operating system resource, SIGPLAN Not. (USA), (2002), 123 - 32, [abs]
  18. Chia-Lin Yang and Lebeck, A., A programmable memory hierarchy for prefetching linked data structures, High Performance Computing. 4th International Symposium, ISHPC 2002. Proceedings (Lecture Notes in Computer Science Vol.2327), (2002), 160 - 74, [abs]
  19. Lebeck, A.R. and Koppanalil, J. and Tong Li and Patwardhan, J. and Rotenberg, E., A large, fast instruction window for tolerating cache misses, Proceedings 29th Annual International Symposium on Computer Architecture, (2002), 59 - 70, [ISCA.2002.1003562], [abs]
  20. Chatterjee, S. and Parker, E. and Hanlon, P.J. and Lebeck, A.R., Exact analysis of the cache behavior of nested loops, Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), (2001), 286 - 297, [378795.378859], [abs]
  21. Srinivasan, S.T. and Ju, R.D. and Lebeck, A.R. and Wilkerson, C., Locality vs. criticality, Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, (2001), 132 - 143, [379240.379258], [abs]
  22. Fan, X. and Ellis, C.S. and Lebeck, A.R., Memory controller policies for DRAM power management, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, (2001), 129 - 134, [abs]
  23. Srinivasan, S.T. and Dz-Ching Ju, R. and Lebeck, A.R. and Wilkerson, C., Locality vs. criticality, Proceedings 28th Annual International Symposium on Computer Architecture, (2001), 132 - 43, [ISCA.2001.937442], [abs]
  24. Hanlon, P.J. and Chung, D. and Chaterjee, S. and Genius, D. and Lebeck, A.R. and Parker, E., The combinatorics of cache misses during matrix multiplication, Journal of Computer and System Sciences, (2001), 80 - 126, [1756], [abs]
  25. Thottethodi, M. and Lebeck, A.R. and Mukherjee, S.S., Self-tuned congestion control for multiprocessor networks, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, (2001), 107 - 18, [HPCA.2001.903256], [abs]
  26. Chatterjee, S. and Parker, E. and Hanlon, P.J. and Lebeck, A.R., Exact analysis of the cache behavior of nested loops, SIGPLAN Not. (USA), (2001), 286 - 97, [abs]
  27. Chia-Lin Yang and Sano, B. and Lebeck, A.R., Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions, IEEE Trans. Comput. (USA), (September, 2000), 934 - 46, [12.869324], [abs]
  28. Lebeck, A.R. and Xiaobo Fan and Heng Zeng and Ellis, C., Power aware page allocation, Oper. Syst. Rev. (USA), (2000), 105 - 16, [abs]
  29. Chia-Lin Yang and Lebeck, A.R., Push vs. pull: data movement for linked data structures, Conference Proceedings of the 2000 International Conference on Supercomputing, (2000), 176 - 86, [abs]
  30. Lebeck, A.R. and Fan, X. and Zeng, H. and Ellis, C., Power aware page allocation, International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, (2000), 105 - 116, [378993.379007], [abs]
  31. Chatterjee, S. and Lebeck, A.R. and Patnala, P.K. and Thottethodi, M., Recursive array layouts and fast parallel matrix multiplication, SPAA'99. Eleventh Annual ACM Sympsoium on Parallel Algorithms and Architectures, (1999), 222 - 31, [305619.305645], [abs]
  32. Lebeck, A.R. and Raymond, D.R. and Chia-Lin Yang and Thottethodi, H.S., Annotated memory references: a mechanism for informed cache management, Euro-Par'99. Parallel Processing. 5th International Euro-Par Conference. Proceedings (Lecture Notes in Computer Science Vol.1685), (1999), 1251 - 4, [abs]
  33. Chatterjee, S. and Jain, V.V. and Lebeck, A.R. and Mundhra, S. and Thottethodi, M., Nonlinear array layouts for hierarchical memory systems, Conference Proceedings of the 1999 International Conference on Supercomputing, (1999), 444 - 53, [305138.305231], [abs]
  34. Lebeck, A.R., Cache conscious programming in undergraduate computer science, SIGCSE Bull. (USA), (1999), 247 - 51, [384266.299772], [abs]
  35. Srinivasan, S.T. and Lebeck, A.R., Load latency tolerance in dynamically scheduled processors, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, (1998), 148 - 59, [MICRO.1998.742777], [abs]
  36. Chia-Lin Yang and Sano, B. and Lebeck, A.R., Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture, (1998), 14 - 24, [MICRO.1998.742765], [abs]
  37. Thottethodi, M. and Chatterjee, S. and Lebeck, A.R., Tuning Strassen's matrix multiplication for memory efficiency, Proceedings of ACM/IEEE SC98: 10th Anniversary. High Performance Networking and Computing Conference (Cat. No. RS00192), (1998), 14 pp. -, [abs]
  38. Yocum, K.G and Chase, J.S. and Gallatin, A.J. and Lebeck, A.R., Cut-through delivery in trapeze: an exercise in low-latency messaging, IEEE International Symposium on High Performance Distributed Computing, Proceedings, (1997), 243 - 252, [HPDC.1997.626425], [abs]
  39. Lebeck, A.R. and Wood, D.A., Active memory: a new abstraction for memory system simulation, ACM Trans. Model. Comput. Simul. (USA), (1997), 42 - 77, [244804.244806], [abs]
  40. Lebeck, A.R. and Wood, D.A., Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors, Proceedings 22nd Annual International Symposium on Computer Architecture (IEEE Cat. No.95CB35801), (1995), 48 - 59, [ISCA.1995.524548], [abs]
  41. Lebeck, A.R. and Wood, D.A., Active memory: a new abstraction for memory-system simulation, Perform. Eval. Rev. (USA), (1995), 220 - 30, [abs]
  42. Lebeck, A.R. and Sohi, G.S., Request combining in multiprocessors with arbitrary interconnection networks, IEEE Trans. Parallel Distrib. Syst. (USA), (1994), 1140 - 55, [71.329673], [abs]
  43. Schoinas, I. and Falsafi, B. and Lebeck, A.R. and Reinhardt, S.K. and Larus, J.R. and Wood, D.A., Fine-grain access control for distributed shared memory, SIGPLAN Not. (USA), (1994), 297 - 306, [abs]
  44. Lebeck, A.R. and Wood, D.A., Cache profiling and the SPEC benchmarks: a case study, Computer (USA), (1994), 15 - 26, [2.318580], [abs]
  45. Falsafi, B. and Lebeck, A.R. and Reinhardt, S.K. and Schoinas, I. and Hill, M.D. and Larus, J.R. and Rogers, A. and Wood, D.A., Application-specific protocols for user-level shared memory, Proceedings Supercomputing '94 (Cat. No.94CH34819), (1994), 380 - 9, [SUPERC.1994.344301], [abs]
  46. Reinhardt, S.K. and Hill, M.D. and Larus, J.R. and Lebeck, A.R. and Lewis, J.C. and Wood, D.A., The Wisconsin Wind Tunnel: virtual prototyping of parallel computers, Perform. Eval. Rev. (USA), (1993), 48 - 60, [abs]
  47. Wood, D.A. and Chandra, S. and Falsafi, B. and Hill, M.D. and Larus, J.R. and Lebeck, A.R. and Lewis, J.C. and Mukherjee, S.S. and Palacharla, S. and Reinhardt, S.K., Mechanisms for cooperative shared memory, Comput. Archit. News (USA), (1993), 156 - 67, [173682.165151], [abs]
  48. Kessler, R.E. and Jooss, R. and Lebeck, A. and Hill, M.D., Inexpensive implementations of set-associativity, 16th Annual International Symposium on Computer Architecture (Cat. No.89CH2705-2), (1989), 131 - 9, [74925.74941], [abs]
  49. Hill, M.D. and Larus, J.R. and Lebeck, A.R. and Talluri, M. and Wood, D.A., Wisconsin Architectural Research Tool Set, Comput. Archit. News (USA), (0), 8 - 10, [165496.165500], [abs]

Other

  1. X. Fan, C S. Ellis, A. R. Lebeck, The Synergy between Power-aware Memory Systems and Processor Voltage Scaling (PACS 03), Workshop on Power Aware Computing Systems, (2003), Springer-Verlag Lecture Notes in Computer Science, [pdf],