Daniel J. Sorin
Professor of Computer Science
Dr. Daniel Sorin is the Addy Professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.
Appointments and Affiliations
- Professor of Electrical and Computer Engineering
- Professor of Computer Science
- Office Location: 209C Hudson Hall, Durham, NC 27708
- Office Phone: (919) 660-5439
- Email Address: email@example.com
- Ph.D. University of Wisconsin at Madison, 2002
- M.S. University of Wisconsin at Madison, 1998
- B.S. Duke University, 1996
Computer architecture, designing microarchitectures so that they are easier to verify, improving computer system fault tolerance, developing memory systems for multicore processors, and designing special-purpose accelerators
Awards, Honors, and Distinctions
- Program Chair of HiPEAC 2017. HiPEAC. 2017
- Co-chair of selection committee for IEEE Micro's Top Picks 2016. IEEE Micro. 2016
- Associate Editor in Chief. Computer Architecture Letters. 2015
- IEEE Micro Top Pick. IEEE Micro. 2015
- Best Paper Award. 20th International Symposium on High Performance Computer Architecture. 2014
- IEEE Micro Top Pick. IEEE Micro. 2011
- Lois and John L. Imhoff Distinguished Teaching Award. Pratt School of Engineering. 2011
- ACM Senior Member. Association for Computing Machinery. 2009
- Eta Kappa Nu. Unknown. 2008
- Intel Graduate Fellowship. Unknown. 2008
- NSF Early CAREER Award. National Science Foundation. 2008
- Outstanding Graduate Research Award. University of Wisconsin. 2008
- Phi Beta Kappa. Unknown. 2008
- Tau Beta Pi. Unknown. 2008
- Top of 2004 - Nanocomputing Research. Technology Research News. 2008
- Faculty Early Career Development (CAREER) Program. National Science Foundation. 2005
- COMPSCI 250D: Computer Architecture
- ECE 250D: Computer Architecture
- ECE 552: Advanced Computer Architecture I
- ECE 554: Fault-Tolerant and Testable Computer Systems
- Mappouras, G; Vahid, A; Calderbank, R; Sorin, DJ, Extending flash lifetime in embedded processors by expanding analog choice, Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems, vol 37 no. 11 (2018), pp. 2462-2473 [10.1109/TCAD.2018.2857059] [abs].
- Oswald, N; Nagarajan, V; Sorin, DJ, ProtoGen: Automatically generating directory cache coherence protocols from atomic specifications, Proceedings International Symposium on Computer Architecture (2018), pp. 247-260 [10.1109/ISCA.2018.00030] [abs].
- Sorin, DJ, Low-Power Content Addressable Memory, Computer, vol 51 no. 3 (2018), pp. 8-9 [10.1109/MC.2018.1731073] [abs].
- Mappouras, G; Vahid, A; Calderbank, R; Hower, DR; Sorin, DJ, Jenga: Efficient fault tolerance for stacked DRAM, Proceedings 35th Ieee International Conference on Computer Design, Iccd 2017 (2017), pp. 361-368 [10.1109/ICCD.2017.62] [abs].
- Matthews, O; Sorin, DJ, Architecting hierarchical coherence protocols for push-button parametric verification, Proceedings of the Annual International Symposium on Microarchitecture, Micro, vol Part F131207 (2017), pp. 477-489 [10.1145/3123939.3123971] [abs].