Daniel J. Sorin

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W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering

Dr. Daniel Sorin is the W.H. Gardner Jr. associate professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.

Appointments and Affiliations
  • W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
  • Associate Professor of Electrical and Computer Engineering
Contact Information:

  • M.S. University of Wisconsin at Madison, 1998
  • B.S. Duke University, 1996

Research Interests:

The primary focus of my research is computer architecture. This research includes work to: improve the dependability of computer architectures, design microarchitectures such that their designs are easier to validate, and develop memory system designs for multicore processors.


Computer Engineering
Computer Architecture
Fault Tolerance

Awards, Honors, and Distinctions:

  • Top Picks in Computer Architecture, 2015, 2010, 2007
  • Best Paper, HPCA, 2014
  • Lois and John L. Imhoff Distinguished Teaching Award, 2011
  • NSF Early CAREER Award, National Science Foundation, 2005
  • Outstanding Graduate Research Award, University of Wisconsin
  • Phi Beta Kappa
  • Tau Beta Pi
  • Top of 2004 - Nanocomputing Research, Technology Research News

Courses Taught:
  • ECE 250L: Computer Architecture
  • ECE 552: Advanced Computer Architecture I
  • ECE 554: Fault-Tolerant and Testable Computer Systems
  • ECE 652: Advanced Computer Architecture II

Representative Publications: (More Publications)
    • Sorin, DJ; Matthews, O; Zhang, M, Architecting dynamic power management to be formally verifiable, Design Automation Conference (2014) [10.1145/2593069.2596669] [abs].
    • Zhang, M; Bingham, JD; Erickson, J; Sorin, DJ, PVCoherence: Designing flat coherence protocols for scalable verification (2014), pp. 392-403 [10.1109/HPCA.2014.6835949] [abs].
    • Nathan, R; Sorin, DJ, Nostradamus: Low-cost hardware-only error detection for processor cores, Design, Automation and Test in Europe Conference and Exhibition , IEEE (2014) [abs].
    • Hechtman, BA; Sorin, DJ, Evaluating cache coherent shared virtual memory for heterogeneous multicore chips, ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software (2013), pp. 118-119 [10.1109/ISPASS.2013.6557152] [abs].
    • Hechtman, BA; Sorin, DJ, Exploring memory consistency for massively-threaded throughput-oriented processors (2013), pp. 201-212 [10.1145/2485922.2485940] [abs].