Daniel J. Sorin
W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
Dr. Daniel Sorin is the W.H. Gardner Jr. associate professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.
Appointments and Affiliations
- W. H. Gardner, Jr. Associate Professor Electrical & Computer Engineering
- Associate Professor of Electrical and Computer Engineering
- Associate Professor in the Department of Computer Science
- Office Location: 209C Hudson Hall, Durham, NC 27708
- Office Phone: (919) 660-5439
- Email Address: email@example.com
- Web Page:
- M.S. University of Wisconsin at Madison, 1998
- B.S. Duke University, 1996
The primary focus of my research is computer architecture. This research includes work to: improve the dependability of computer architectures, design microarchitectures such that their designs are easier to validate, and develop memory system designs for multicore processors.
Awards, Honors, and Distinctions:
- Eta Kappa Nu
- Intel Graduate Fellowship
- NSF Early CAREER Award, National Science Foundation, 2005
- Outstanding Graduate Research Award, University of Wisconsin
- Phi Beta Kappa
- Tau Beta Pi
- Top of 2004 - Nanocomputing Research, Technology Research News
- COMPSCI 550: Advanced Computer Architecture I
- COMPSCI 550: Introduction to Numerical Methods and Analysis
- COMPSCI 650: Advanced Computer Architecture II
- ECE 250L: Computer Architecture
- ECE 552: Advanced Computer Architecture I
- ECE 652: Advanced Computer Architecture II
Representative Publications: (More Publications)
- Hechtman, BA; Sorin, DJ, Evaluating cache coherent shared virtual memory for heterogeneous multicore chips, ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software (2013), pp. 118-119 [10.1109/ISPASS.2013.6557152] [abs].
- Hechtman, BA; Sorin, DJ, Exploring memory consistency for massively-threaded throughput-oriented processors, Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA (2013), pp. 201-212 [10.1145/2485922.2485940] [abs].
- Jacobvitz, AN; Calderbank, R; Sorin, DJ, Coset coding to extend the lifetime of memory, IEEE High-Performance Computer Architecture Symposium Proceedings (2013), pp. 222-233 [10.1109/HPCA.2013.6522321] [abs].
- Martin, MMK; Hill, MD; Sorin, DJ, Why on-chip cache coherence is here to stay, Communications of the ACM, vol 55 no. 7 (2012), pp. 78-89 [10.1145/2209249.2209269] [abs].
- Jacobvitz, AN; Calderbank, R; Sorin, DJ, Writing cosets of a convolutional code to increase the Lifetime of Flash memory, 2012 50th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2012 (2012), pp. 308-318 [10.1109/Allerton.2012.6483234] [abs].