ECE 252 / CPS 220 - Advanced Computer Architecture I

ECE 252 / CPS 220

Advanced Computer Architecture I

Fall 2005

Professor Daniel J. Sorin

Objectives

The objective of this course is to learn the fundamental aspects of computer architecture design and analysis.

The course focuses on processor design, pipelining, superscalar, out-of-order execution, caches (memory hierarchies), virtual memory, storage

systems, and simulation techniques. Advanced topics include a survey of parallel architectures and future directions in computer architecture.

Prerequisites: ECE 152, CPS 104, or consent of instructor.

Class Location and Hours

Class meets Monday/Wednesday/Friday from 10:20am - 11:10am.

Location: 207 Hudson Hall (note the change!!)

Instructor, Teaching Assistant, and News Group

Professor Daniel J. Sorin

Office: 1111 Hudson Hall (will be moving to 209C Hudson on Sept 6)

Office Hours: Mon 1:30-2:30, Thurs 3:00-4:00

Email: sorin AT ee DOT duke DOT edu (email subject must begin with ECE252)

Teaching Assistant: Anita Lungu

Office: D311 LSRC

Office Hours: Weds 2-3pm and Fri 1-2pm

Email: anita AT cs DOT duke DOT edu

Class News Group: duke.courses.ece252

You are responsible for checking this newsgroup. Please consult it before emailing the TA or professor.

Required Textbook

Computer Architecture: A Quantitative Approach, 3rd edition, by Hennessy and Patterson

Assignments and Grading

This course will require readings from the textbooks and from selected research papers. While you will not be quizzed on readings, you

should still be certain to have read them before class so that you can learn from the class. And, to appeal to your practical side, all readings are

fair game for the exams. Added bonus: you will be better at reading research papers at the end of this class than at the beginning.

Students are responsible for:

homework - 30% of grade
midterm exam - 15% of grade (midterm from fall 2003)
final exam - 25% of grade (final from fall 2003)
individual or group project (including proposals and presentations) - 30% of grade

Note to Computer Science students: Qualifying grade is based only on the midterm and final.

Late policy for homework and project (except for dean's excuses):

Homework: <1 day late = 50% off

>1 day late = 0

Project: No late projects will be accepted!

Academic Misconduct: I will not tolerate academically dishonest work. This includes cheating on the exams and plagiarism on the project.

Be careful on the project to cite prior work and to give proper credit to others' research.

Refer to the Duke Undergraduate Honor Code or to the instructor if you have any questions about misconduct.

Topics, Lecture Notes, and Reading Assignments (still in flux!!)

I will post lecture notes (in PDF format) shortly before I cover them in class. Click on topic title for link to notes.

Readings in blue will be provided by the instructor (click on links below for PS or PDF).

Topic	Reading Assignments
Course Introduction & Fundamentals of Computer Design and Evaluation	H/P Chapter 1
Instruction Sets	H/P Chapter 2; CISC vs. RISC; Transmeta Crusoe
Pipelined Processors	H/P Appendix A (except A.8); Optimal Pipeline Depth; Designing for Power
Hardware/Dynamic Exploitation of Instruction Level Parallelism Superscalar Execution Dynamic Scheduling: Scoreboard and Tomasulo Dynamic Scheduling: Speculation and Precise Interrupts	H/P 3.1, A.8, 3.2-3.15; MIPS R10000; Complexity-Effective Superscalar; Checkpoint Processing and Recovery; DIVA
Software/Static Exploitation of Instruction Level Parallelism	H/P Chapter 4; EPIC/IA-64
Memory Systems Storage Hierarchy Principles and Caches Main Memory	H/P Chapter 5; NUCA; Value Prediction
I/O	H/P Chapter 7; RAID; QPIP
Multithreading and Multiprocessors	H/P Chapter 6; SMT; Multiscalar

Homework

Homework #0: Due Wednesday, August 31 in class

Homework #1: Due Wednesday, Sept 14 in class (question 7 due electronically at 10:00am)

Homework #2: Due Wednesday, Sept 28 in class (question 6 due electronically at 10:00am)

Homework #3: Due Friday, Oct 14 in class

Homework #4: Due Wednesday, Nov 9 in class (question 7 due electronically at 10:00am)

Homework #5: Due Monday, Nov 21 in class

Project

The course project will be performed either individually or in groups of 2 or 3.

Projects will explore a micro-architectural issue (of your choice) using SimpleScalar. You will be expected to modify the code in sim-outorder as part of your project. Look here for project guidelines and ideas.

Project proposals (2 pages max!!): Due Friday, Oct 28. Proposals must contain the following information:

goal of the project
how the experiments will be performed
timeline for expected project milestones
brief summary of related research papers (with appropriate references!)

Project reports (15 pages max!!): Due Monday, Dec 5 in class. No exceptions!

Schedule (tentative)

This is a tentative schedule which may change depending on time constraints and which days the instructor will be out of town.

Week	Monday	Wednesday	Friday
Aug 29	Intro/Start Fundamentals (Ch 1)	End Fundamentals	Start Instruction Sets (Ch 2)
Sept 5	Instruction Sets	End Instruction Sets	Start Pipelining (App A)
Sept 12	Pipelining	End Pipelining	Start Dynamic ILP (Ch 3)
Sept 19	Dynamic ILP	Dynamic ILP	Dynamic ILP
Sept 26	Dynamic ILP	Dynamic ILP	Dynamic ILP
Oct 3	Dynamic ILP	Dynamic ILP	Dynamic ILP
Oct 10	FALL BREAK	Start Static ILP (Ch 4)	Static ILP
Oct 17	End Static ILP	REVIEW FOR MIDTERM	MIDTERM
Oct 24	Start Memory Systems (Ch 5)	Memory Systems	Memory Systems
Oct 31	Memory Systems	Memory Systems	End Memory Systems
Nov 7	Start I/O (Ch 7)	I/O	End I/O
Nov 14	Start Multithreading (Ch 6)	Multithreading	Multithreading
Nov 21	Multithreading	THANKSGIVING BREAK
Nov 28	Advanced Topics	Advanced Topics	REVIEW FOR FINAL
Dec 5	PROJECT PRESENTATIONS
Dec 12	*-------- EXAM WEEK --------*